Design, Analysis, and Optimization of Radio Frequency Front-ends for Integrated Wireless Receivers

Monograph Article dissertation (summary + original articles) Department Laboratory Field of research Opponent(s) Supervisor (Instructor) Abstract Keywords radio frequency, radio receiver, direct conversion, low-noise amplifier, downconversion mixer Design, analysis, and optimization of radio frequency front-ends for integrated wireless receivers X This thesis consists of six publications and an overview of the research topic, which is also a summary of the work. The research described in this thesis is focused on the design, analysis, and optimization of RF front-ends for wireless zero-and low-IF receivers. The main interest of the work is in the 1-4 GHz range and in CMOS and BiCMOS technologies. Often, the RF front-end limits the performance of the entire direct conversion or low-IF radio receiver. The emphasis in this work is on the challenges posed by mass production for the design of integrated RF circuits. Thus, the effects of packaging and ESD protection on the LNA performance are analyzed and circuit optimization and design methods for the packaged LNAs are examined. This thesis also studies circuit techniques for the stabilization of the RF front-end performance against process and temperature variations. For this purpose, a gain stabilization technique for tuned LNAs is proposed. By applying the proposed method, the voltage gain variation of the inductively degenerated LNA, which is the most popular LNA architecture, is shown to be reduced several decibels. As a consequence, the radio receiver can more easily meet its specifications in the presence of IC process variations and the product yield is thereby improved. To improve the IIP2 of the mixer, a circuit technique for the cancellation of the second-order intermodulation distortion in downconversion mixer RF input stages is proposed. The presented method is shown to improve the yield of the radio receiver by reducing the IIP2 sensitivity to mismatches and offsets. Low supply voltage and low-frequency flicker noise present in sub-micron CMOS processes pose challenges for the design of direct conversion RF front-ends, especially for narrow-band systems such as GSM. However, since the development of low-voltage CMOS analog and RF circuits is economically advantageous, the design and optimization of low-voltage CMOS RF front-ends are studied in this work. The work summarizes the design, analysis, and optimization of several RF front-ends, LNAs, and mixers. One of the implemented RF front-ends is integrated with an on-chip VCO as a part of larger direct conversion receiver chip. One is realized with an on-chip VCO as a standalone RF …